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white electronic designs corporation ? (508) 366-5151 www.whiteedc.com 128kx24 asynchronous sr 128kx24 asynchronous sr 128kx24 asynchronous sr 128kx24 asynchronous sr 128kx24 asynchronous sr am, 5v am, 5v am, 5v am, 5v am, 5v
the edi8l24128cxxbc is a 5v, three megabit sram con- structed with three 128kx8 die mounted on a multi-layer laminate substrate. with 12 to 15ns access times, x24 width and a 5v operating voltage, the edi8l2418c is ideal for creating a single chip memory solution for the motorola dsp5600x or a two chip solution for the analog devices sharc? dsp. the single or dual chip memory solutions offer improved system performance by reducing the length of board traces and the number of board connections compared to using multiple monolithic devices. for example, the capacitance load on the data lines for the bga package is 58% less than a monolithic soj solution. the jedec standard 119 lead bga provides a 44% space savings over using 128kx8, 300mm wide sojs and the bga package has a height of 100mm compared to 148mm for the soj packages. 128kx24 bit cmos static random access memory array fast access times: 12 and 15ns master output enable and write control ttl compatible inputs and outputs fully static, no clocks surface mount package 119 lead bga (jedec mo-163), no. 391 small footprint, 14mm x 22mm multiple ground pins for maximum noise immunity single +5v (10%) supply operation dsp memory solution motorola dsp5600x? analog devices sharc?

1234567 anca 0 a 1 a 2 a 3 a 4 nc bnca 5 a 6 ea 7 a 8 nc cdq 12 nc nc nc nc nc dq 0 ddq 13 v cc gnd gnd gnd v cc dq 1 edq 14 gnd v cc gnd v cc gnd dq 2 fdq 15 v cc gnd gnd gnd v cc dq 3 gdq 16 gnd v cc gnd v cc gnd dq 4 hdq 17 v cc gnd gnd gnd v cc dq 5 i nc gnd v cc gnd v cc gnd nc jdq 18 v cc gnd gnd gnd v cc dq 6 kdq 19 gnd v cc gnd v cc gnd dq 7 ldq 20 v cc gnd gnd gnd v cc dq 8 mdq 21 gnd v cc gnd v cc gnd dq 9 ndq 22 v cc gnd gnd gnd v cc dq 10 odq 23 nc nc nc nc nc dq 11 pnca 9 a 10 wa 11 a 12 nc qnca 13 a 14 ga 15 a 16 nc a 0-16 address inputs e chip enables w master write enable g master output enable dq 0-23 common data input/output v cc power (+5v10%) gnd ground nc no connection january 2002 rev. 1 eco# 14691
white electronic designs corporation westborough, ma (508) 366-5151

voltage on any pin relative to v ss -0.5v to 7.0v operating temperature t s (ambient) commercial 0c to + 70c industrial -40c to +85c storage temperature -55c to +125c power dissipation 3 watts output current. 20 ma junction temperature, t j 175c *stress greater than those listed under "absolute maximum ratings" may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability.

note: for t ehqz , t ghqz and t wlqz , cl = 5pf figure 2 parameter symbol min typ max units supply voltage v cc 4.5 5.0 5.5 v supply voltage v ss 00 0v input high voltage v ih 2.2 ? vcc+0.3 v input low voltage vil -0.3 ? +0.8 v

input pulse levels v ss to 3.0v input rise and fall times 5ns input and output timing levels 1.5v output load figure 1 parameter symbol max unit address lines c l 8pf data lines c d / q 10 pf write & output enable line w, g 8 pf chip enable lines e 8 pf

h x x standby high z i cc 2 , i cc 3 l h h output deselect high z i cc 1 l h l read data out i cc 1 l l x write data in i cc 1

operating power supply current i cc 1 w = v il , i i / o = 0ma, min cycle 200 270 ma standby (ttl) power supply current i cc 2 e v ih , v in v il or v in v ih ,45ma f = 0mhz full standby power cmos i cc 3 e v cc -0.2v 10 ma supply current v in v cc -0.2v or v in 0.2v input leakage current i li v in = 0v to v cc ? ? 10 a output leakage current i lo v i / o 0v to v cc ? ? 10 a output high voltage v oh i oh = -4.0ma 2.4 ? ? v output low voltage v ol i ol = 8.0ma ? ? 0.4 v
white electronic designs corporation (508) 366-5151 www.whiteedc.com
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read cycle time t avav t rc 12 15 ns address access time t avqv t aa 12 15 ns chip enable access time t elqv t acs 12 15 ns chip enable to output in low z 1 t elqx t clz 33 ns chip disable to output in high z 1 t ehqz t chz 67ns output hold from address change t avqx t oh 33 ns output enable to output valid t glqv t oe 67ns output enable to output in low z 1 t glqx t olz 00 ns output disable to output in high z 1 t ghqz t ohz 67ns 1. this parameter is guaranteed by design but not tested.
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write cycle time t avav t wc 12 15 ns chip enable to end of write t elwh t cw 99ns t eleh t cw 99ns address setup time t avwl t as 00ns t avel t as 00ns address valid to end of write t avwh t aw 910ns t aveh t aw 910ns write pulse width t wlwh t wp 10 11 ns t eleh t wp 10 11 ns write recovery time t whax t wr 00ns t ehax t wr 00ns data hold time t whdx t dh 00ns t ehdx t dh 00ns write to output in high z 1 t wlqz t whz 060 7ns data to write time t dvwh t dw 67ns t dveh t dw 67ns output active from end of write 1 t whqx t wlz 33ns 1. this parameter is guaranteed by design but not tested.
white electronic designs corporation westborough, ma (508) 366-5151

read cycle 2 (w high) read cycle 1 (w high; g, e low) write cycle 1, w controlled write cycle 2, e controlled
white electronic designs corporation (508) 366-5151 www.whiteedc.com !
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edi8l24128c12bi 12 391 edi8l24128c15bi 15 391 industrial (-40 c to +85c) all dimensions are in inches

EDI8L24128C12BC 12 391 edi8l24128c15bc 15 391 commercial (0 c to +70c)

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